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AR# 20894

8.1i XST - "WARNING:Xst:2189 - "file.vhd" line xx: Conflict on property <property_name> of instance <inst> between generic and attribute"


Keywords: primitive, VHDL, Verilog, meta, comment, pass, 7.1i

When I set an attribute on a primitive, XST issues a warning indicating a possible simulation mismatch:



component FD
port (D : in std_logic;
C : in std_logic;
Q : out std_logic);
end component;

-- INIT is a generic attached
-- to the FD primitive
attribute init : string;
attribute init of u1 : label is "0";


u1 : FD port map (Q=>q, C=>c, D=>d);

XST issues warning messages for attributes that have corresponding generics on the primitives. The warning message is issued because attributes are not supported for simulation. When the attribute modifies the behavior of the primitive to which it is attached, a generic must still be added for proper simulation of the primitive.


XST now supports modifying the properties of primitives through generics. If the above warning message was generated as a result of Architecture Wizard or ECS, you can safely ignore the warning message. You can filter out the warning messages through ISE. For more information, search for "filtering" in the ISE pull-down Help menu.

XST supports modifying the properties of primitives through generics/parameters as follows:



u1 : FD
generic map (INIT => '0')
port map (Q => q, C => c, D => d);
AR# 20894
Date 01/07/2009
Status Archive
Type General Article