How much time is needed in a JTAG configuration?
The time needed in a JTAG configuration is related to both device size and the TCK speed.
1. On power-up, place a logic 1 on the TMS, and clock the TCK five times to ensure starting in the TLR (Test-Logic-Reset) state (five TCK cycles).
2. Move into the RTI state (one TCK cycle).
3. Move into the SELECT-IR state (two TCK cycles).
4. Enter the SHIFT-IR state (two TCK cycles).
5. Start loading the CFG_IN instruction, LSB first: 111000101(nine TCK cycles).
6. Load the MSB of CFG_IN instruction when exiting SHIFT-IR, as defined in the IEEE standard (one TCK cycle).
7. Enter the SELECT-DR state (two TCK cycles).
8. Enter the SHIFT-DR state (two TCK cycles).
9. Shift in the Virtex-4 bitstream. Bitn (MSB) is the first bit in the bitstream ((bits in bitstream-1) TCK cycles).
10. Shift in the last bit of the bitstream. Bit0 (LSB) shifts on the transition to EXIT1-DR (one TCK cycle).
11. Enter UPDATE-DR state (one TCK cycle).
12. Reset TAP by clocking five 1s on TMS (five TCK cycles).
13. Enter the SELECT-IR state (two TCK cycles).
14. Move to the SHIFT-IR state (two TCK cycles).
15. Start loading the JSTART instruction. The JSTART instruction initializes the startup sequence. 111001100 (nine TCK cycles).
16. Load the last bit of the JSTART instruction (one TCK cycle).
17. Move to the UPDATE-IR state (one TCK cycle).
18. Move to the RTI state and clock the startup sequence by applying a minimum of 12 clock cycles to the TCK (12 TCK cycles).
19. Move to the TLR state. The device is now functional (three TCK cycles).
Add all of the TCK cycles to get 60+ bits in bitstream TCK cycles. For information on the total number of bits for different devices, refer to the Virtex Series FPGA data sheets at:
The configuration time = (60+ bits in bitstream) / (TCK Frequency)