UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20902

MIG007 Release 5 - I received a synthesis error when I used the XST in ISE

Description

Keywords: Virtex-II, Virtex-II Pro, Virtex-4, MIG 007, XST, Synthesis, Properties

Urgency: Standard

General Description:
A few items must be configured when synthesizing with XST. These should be added to the run options of the XST and implementation script, or set through the Project Navigator GUI.

Solution

The following are the options to set in ISE GUI:

Synthesize-XST properties:

Synthesis Options:

Optimization Goal ---> Speed
Optimization Effort ---> High
synthesis Constraints File ---> N/A
Use synthesis Constraints File ---> unchecked
Library Search Order --->
Keep Hierarchy ---> Yes
Global Optimization Goal ---> AllClockNets
Generate RTL Schematic ---> Yes
Read Cores ---> checked
cores Search Directories --->
Write Timing Constraints ---> unchecked
Cross Cloak Analysis ---> unchecked
Hierarchy Separator ---> /
Bus Delimiter ---> ()
Slice Utilization Ratio ---> 100
Case ---> Maintain
Work Direcotory ---> ./xst
HDL INI File --->
Verilog2001 ---> checked


HDL Options: No need to change any Options(Default)


Xilinx Specific Options:

Add I/O Buffers ---> checked
Max Fanout ---> 500
Number of clock Buffers ---> 16
Register Duplication ---> unchecked
Equivalent Register Removal ---> unchecked
Register Balancing ---> No
Move First Flip-Flop Stage ---> N/A
Move Last Flip-Flop Stage ---> N/A
Pack I/O Registers into IOBs ---> No
Slice Packing ---> unchecked
Convert Tristates to Logic ---> No
Optimize Instantiated Primitives ---> unchecked


Translate Properties:

Use LOC Constraints ---> checked
Netlist Translation Type ---> Timestamp
Macro Search Path
Create I/O Pads from Ports ---> unchecked
Allow Unexpanded Blocks ---> checked
User Rules File for Netlist Launcher
Allow Unmatched LOC Constrains ---> unchecked
Preserve Hierarchy on Sub Module ---> unchecked
Other Ngdbuild Command Line Options

Map Properties:

Perform Timing Driven Packing and Placement ---> checked
Map Effort Level ---> High
Trim Unconnected Signals ---> checked
Replicate Logic to Allow Logic Level Reduction ---> checked
Allow Logic Optimization Across Hierarchy ---> checked
Map to Input Functions ---> 4
Optimization Strategy(Cover Mode) ---> Speed
Generate Detailed MAP Report ---> checked
MAP Guide Design File(.ncd)
MAP Guide Mode ---> None
Convert Guide File to 6.1iFormat ---> unchecked
Use RLOC Constraints ---> checked
Pack I/O Register/Latches into IOBs ---> Off
Disable Register Ordering ---> unchecked
CLB Pack Factor Percentage ---> 100
Tri-state Buffer Transformation Mode ---> Off
Map Slice Logic into Unused Block RAMs ---> unchecked
Other Map Command Line Options


Place & Route Properties:

Place & Route Effort Level(Overall) ---> High
Placer Effort Level(Overrides Overall Level) ---> High
Router Effort Level(Overrides Overall Level) ---> High
Extra Effort (Highest PAR level only) ---> None
Starting Placer Cost Table(1-100) ---> 1
Place And Route Mode ---> Normal Place and Route
PAR Guide Design File(.ncd)
PAR Duide Mode ---> None
Convert Guide File to 61i Format ---> unchecked
Use Timing Constrains ---> checked
Use Bonded I/Os ---> unchecked
Generate Asynchronous Delay Report ---> unchecked
Generate Place & Route Static Timing Report ---> checked
Generate Place & Route Simulation Model ---> unchecked
Other Place & Route Command Line Options



When running XST in Command Line, you need to set the following options:

-hierarchy_separator /
-keep_hierarchy YES
-register_duplication NO
-equivalent_register_removal NO
-slice_packing NO

Also, in MAP, the following option should be set:
Command line: map -ignore_keep_hierarchy

AR# 20902
Date Created 09/03/2007
Last Updated 04/06/2009
Status Archive
Type General Article