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AR# 20920

7.1i Schematic - Bus width of pin I and O is incorrect in symbol ICAP_VIRTEX4


Keywords: input, output, icap, 32, 8

Urgency: Standard

General Description:
In the Xilinx Schematic Editor, the ICAP_VIRTEX4 symbol has an I and O pin with a bus width of 8. The width should be 32.


This problem has been fixed in the latest 7.1i Service Pack available at:
The first service pack containing the fix is 7.1i Service Pack 1.
AR# 20920
Date 03/19/2006
Status Archive
Type General Article
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