We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20940

7.1i NGDBuild CoolRunner-II - TNM constraints on the input of "clk_div2r" clock divider does not propagate to the outputs


Keywords: Translate, constraint, XdmHelpers, 650, 644, 625

Urgency: Standard

General Description:
I receive the following error when running Translate on my CoolRunner-II design when I am trying to constrain the input to a clk_div2r. What is happening?

WARNING:XdmHelpers:625 - No instances driven from the following signals or pins
are valid for inclusion in TNM group "CLK_IN". A TNM property on a pin or
signal marks only the flip-flops, latches and/or RAMs which are directly or
indirectly driven by that pin or signal.
signal "clk_in"
WARNING:XdmHelpers:644 - No appropriate elements were found for the TNM group
"CLK_IN". This group has been removed from the design.
ERROR:XdmHelpers:650 - The period specification "TS_CLK_IN" is invalid because
the "CLK_IN" group was removed.


This is caused by the TNM constraint failing to propagate through the clk_div2r.

This is scheduled to be fixed in a future software release. In the meantime, you can work around this by constraining the clk_div2r outputs.

This is applicable only to the clk_div2r primitives. This is not an issue with the other flavors of clock divider primitives in CoolRunner-II.
AR# 20940
Date 02/21/2007
Status Archive
Type General Article