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AR# 20945

MIG 007 Rel5 - Is it necessary for the assertion and deassertion of "user_rst_dqs_div" to match Figure 4-3 in the User Guide?


Keywords: Memory Interface Generator, user_rst_dqs_div, signal, rel5

Does the timing for the rst_dqs_div signal have to match what is shown in Figure 4-3 of the MIG 007 rel5 User Guide?


The rst_dqs_div signal is used to generate the write enable signal for the FIFO capturing data during a read. Because of this, the timing of this signal is critical and does need to match the timing diagram shown in the User Guide. If the rst_dqs_div signal asserts prematurely, erroneous data can be captured data due to glitches. If the rst_dqs_div signal is deasserted prematurely, not all of the data will be registered.
AR# 20945
Date 04/06/2009
Status Archive
Type General Article