General Stepping Questions
Step Capability Questions
What is silicon stepping and how does it work?
Silicon stepping is a user-orderable identification system for Xilinx devices denoting the improvement or addition of device capability. As new steps are released, they automatically replace older stepped devices, causing no disruption in user experience. Stepping usually starts at level 0. Larger step devices are a functional superset of lower steps and, as such, designs for lower step devices can be used in higher step silicon without customer intervention. If a design requires the capabilities of a particular step, customers should order that step and compile a bitstream indicating the step in software. Devices are always marked with the stepping level to identify the step of a particular device.
Xilinx has always been committed to offering customers increased time-to-market advantages over other solutions. Stepping allows that advantage by providing customers the solution they need as soon as it is available.
Because newer device steps are a functional superset of previous device steps, Xilinx can introduce incremental improvements to a device family. This allows an earlier release to production, and therefore, earlier customer design verification and qualification.
Stepping changes are reflected in an update to the data sheet, which triggers an Alert to be sent out. For information about signing up for Alerts, see (Xilinx Answer 19380).
Descriptions of particular step capabilities can be found in the device data sheet at:
Virtex-4 and Spartan-3E are the first devicefamilies to use stepping in ordering codes and on the device markings. However, certain members of the Virtex-II and Virtex-II Pro X device families use stepping in the ISE design tools.
The Virtex-5 device family uses stepping in the device ordering code, with no step setting required in the ISE design tools.
Revisions are used by some companies to keep track of devices, but are often very confusing and require numerous changes to the ordering part number in order to take advantage of new revisions. In addition, customers have to keep track of which revision has which errata and adjust their design as new revisions are released. Stepping removes that problem by ensuring backward compatibility on its stepped devices and a capability (rather than revision) ordering system. Actual device capabilities are always marked on the part so customers know what part they have. Bitstreams created for earlier steps will always work in later step devices, and customers will receive the latest material as they are released without having to worry about recompiling their designs.
When a new step is released, do I need to order the new step?
Generally speaking, no. Steps are minor capability improvements. Many applications will not require the enhancements of a new step, so the standard device will work fine. However, if the particular application requires those enhancements, order later steps as they become available.
Simply order as you do now; XCxxx-xxxC, to receive the standard device. If the capabilities of a particular step are essential to your application, you can order them by appending the step level after the ordering part number. XCxxx-xxxCSn, where "n" is the step required (i.e., XCxxx-xxxCS1 for step level 1).
Orders that do not specify the step will be filled with devices that meet initial production stepping capability. Although a newer stepping can be shipped for a non-stepping order, Xilinx guarantees that these devices are fully compatible and will have no side effects on the design.
SCDs are used for special orders. SCDs do not guarantee backwards compatibility. Steps are backward-compatible with earlier steps and are intended to become the standard device.
Can stepped devices have errata?
If an errata issue is found in a step of silicon, a description for that errata will be issued for that step. The details of the errata might be released as a separate Errata sheet and will be reflected in an updated product data sheet.
Stepped devices from different fab locations function the same.
The portion of the JTAG IDCODE reserved for the device "version" will change when stepping level increases. However, there might be multiple JTAG IDCODEs corresponding to a specific stepping level.
Many features of a new step are hardware capabilities and are already present without making any changes to system design or bitstream. Some capabilities, however, require customization through software. This is easily accomplished by specifying the step in software.
How do I specify a particular stepping level in software?
A step can be specified in software by adding a stepping constraint in the UCF file.
NOTE: n is the target stepping level (ES, SCD1, 0, 1, 2, 3, ...).
Xilinx recommends that customers always set the step of their design in software. If the step is not specified in the UCF file, the software default step for the target device is used.
Yes, you can specify an earlier step in the software and use silicon of a later step. However, the software will not take advantage of any new capabilities that require customization associated with the later step.
Xilinx does not recommend configuring a device of an earlier step with a bitstream created for a later step.
Specify the lowest stepping number, using only capabilities available in that step.
Is there any other information about stepping or different silicon steps?
(Product Change Notification XCN07026) - Transition to Step 1 and New Package Substrate for Select Virtex-5 LXT and SXT FPGA Devices
(Xilinx Answer 21605) - Virtex-4 - Where can I find silicon stepping information specific to the Virtex-4 devices? (FAQ)
(Xilinx Answer 15511) - MAP - Can I set CONFIG STEPPING constraint in an environment variable?
(Xilinx Answer 14359) - XST - How do I pass the STEPPING attribute through HDL in XST?
(Xilinx Answer 14358) - SYNPLIFY - How do I pass the new STEPPING attribute through HDL in Synplify?
(Xilinx Answer 21127) - Virtex-4 DCM - What are the new DCM parameters that have been added to the Virtex-4 Data Sheet?
(Xilinx Answer 13314) - Speedfiles/Timing Analyzer/TRCE - How do I determine the level of multiplier stepping used by timing analysis? (CONFIG STEPPING)
(Xilinx Answer 14339) - Virtex-II MULT18X18 - How do I access enhanced multiplier speed for my design? (CONFIG STEPPING constraint)