When I do timing analysis, there are timing failures, which I believe do not exist because the clock arrival time for the destination clocks is not correct.
The Source clock arrival time is computed correctly:
TIMESPEC PHASE + PERIOD/2 = 1.67 (see UCF) + 2.5 = 4.170 ns.
The Destination clock arrival time is off by PERIOD/2. The arrival time should be:
TIMESPEC PHASE + DCM PHASE_SHIFT + PERIOD/2 = 4.625 + 1.288 + 2.5 = 8.413 ns.
Instead, the PERIOD/2 part is left off and it is calculated as:
TIMESPEC PHASE + DCM PHASE SHIFT = 4.625 + 1.288 = 5.913.
Why do the timing analysis tools produce the wrong clock edge and when is this going to be fixed?
You have is a set of constraints that are related to one another in the following way:
TS_A = 5ns;
TS_B = TS_A / 2 + PHASE 4.625;
TS_C = TS_B * 2 + PHASE 1.289;
To work around this issue, relate TS_C back to TS_A instead of TS_B.
This is scheduled to be fixed in the next major design tools release.