General Descriptions:
Designs using either the PCI v3.0.145 or PCI-X v5.0.095 cores for the Virtex-4 with 7.1i Service Pack 1 might encounter timing violations on the IP Core input setup, input hold, or clock-to-output constraints.
For information regarding failing the input hold requirement, refer to (Xilinx Answer 19377).
For input setup or clock-to-out violations, this is a known issue and is scheduled to be fixed in 7.1i Service Pack 3.
Currently, you can work around this issue by either reverting back to 7.1i or accepting the failures until Service Pack 3 is released.
| AR# 21001 | |
|---|---|
| Date | 05/19/2014 |
| Status | Archive |
| Type | General Article |