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AR# 21005

Virtex-II Pro-X RocketIO - Solutions List

Description

General Description: 

This Answer Record contains a list of all Xilinx Answer Records pertaining to Virtex-II Pro X RocketIO.

Solution

General 

 

(Xilinx Answer 21579) - Virtex-II Pro-X RocketIO - What are the frequency ranges (fmin and fmax) for USRCLK and USRCLK2?

 

Logic Design and Simulation 

 

(Xilinx Answer 15199) - Virtex-II Pro-X RocketIO - Why does PMARXLOCK not assert in simulation? 

(Xilinx Answer 19361) - Virtex-II Pro-X RocketIO - Packet data is corrupted during clock correction when using ES silicon 

(Xilinx Answer 19362) - Virtex-II Pro-X RocketIO - Pro X channel bonding match detection logic is always active in ES silicon 

(Xilinx Answer 19363) - 6.2i Virtex-II Pro-X RocketIO SmartModel - Pro X (GT10) SmartModel does not function correctly on Windows platforms 

(Xilinx Answer 19388) - Virtex-II Pro-X RocketIO - Can a clock be routed from the dedicated BREFCLK pins to the fabric? 

(Xilinx Answer 19409) - Virtex-II Pro-X RocketIO - PMA Attribute Bus output data on TXRUNDISP is inverted 

(Xilinx Answer 20379) - Virtex-II Pro-X RocketIO - External MGT lock control 

(Xilinx Answer 20943) - Virtex II Pro-X, Virtex-4 RocketIO - LOSSOFSYNC signal definition 

(Xilinx Answer 21145) - Virtex-II Pro-X RocketIO - PMARXLOCK behavior in parallel loopback mode 

(Xilinx Answer 21222) - Virtex-II Pro-X RocketIO - What is the lane-to-lane skew between the RocketIO, and how do I control/reduce it? 

(Xilinx Answer 21274) - Virtex-II Pro-X RocketIO - What clock frequencies should I use when simulating 64B66B PMA_SPEED_MODEs? 

(Xilinx Answer 21304) - Virtex-II Pro, Virtex-II Pro-X, Virtex-4 FX RocketIO - Is there any difference in the way the TXINHIBIT signal works in the Virtex-II Pro vs. Virtex-II Pro X vs. Virtex-4 MGTs? 

(Xilinx Answer 21305) - Virtex-II Pro, Virtex-II Pro-X, Virtex-4 FX RocketIO - Is there any difference in the way the TXRESET signal works in the Virtex-II Pro vs. Virtex-II Pro X vs. Virtex-4 MGTs? 

(Xilinx Answer 21331) - Virtex-II Pro, Virtex-II Pro-X, Virtex-4 RocketIO - # Attribute Syntax Error : The Attribute ALIGN_COMMA_MSB on GT* instance *.gt*_1 is set to 0 0. Legal values for this attribute are TRUE or FALSE. 

(Xilinx Answer 21356) - Virtex-II Pro-X, Virtex-4 RocketIO - The Virtex-4 MGT does not channel bond. Why? 

(Xilinx Answer 21369) - Virtex-II Pro-X RocketIO - How do I use the PMA_SPEED_USE and PMA_SPEED_HEX attributes to set a custom mode? 

(Xilinx Answer 21541) - Virtex-II Pro, Virtex-II Pro-X, Virtex-4 RocketIO - Synplify 8.0 - "ERROR:LIT:241 - Attribute MCOMMA_32B_VALUE on GT instance" 

(Xilinx Answer 21745) - Virtex-II Pro-X RocketIO - When reading configuration registers in simulation, why is the data on TXRUNDISP not inverted as in hardware? 

(Xilinx Answer 21816) - Virtex-II Pro-X RocketIO- Where is the second bit of RXCPI?

 

Board 

 

(Xilinx Answer 19699) - Virtex-II Pro, Virtex-II Pro-X, Virtex-4 FX RocketIO - Board Debug Steps 

(Xilinx Answer 20101) - Virtex-II Pro-X RocketIO - Why are there internal AC coupling capacitors in Pro X transceivers? 

(Xilinx Answer 20836) - Virtex-II Pro-X RocketIO - How do I estimate power consumption for the MGT in Virtex-II Pro X? 

(Xilinx Answer 20948) - Virtex-II Pro-X RocketIO - What is a unit interval (UI) that is referred to in the Tgjtt specification in the data sheet? 

(Xilinx Answer 21597) - 7.is2 BitGen, Virtex-II Pro-X RocketIO - Why is the Pro X PMA_SPEED_HEX attribute not working in hardware? 

(Xilinx Answer 21984) - Virtex-II Pro-X RocketIO - What socket is used on the MK322 Board?

 

Standards 

 

(Xilinx Answer 19020) - Virtex-II Pro-X RocketIO - OC-192 support for Engineering Samples (ES)

AR# 21005
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article