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AR# 21049

Embedded Tri-mode Ethernet MAC Wrapper v2.1 - Release Notes and Known Issues for the Embedded Tri-mode Ethernet MAC Wrapper

Description

This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v2.1, released in 7.1i IP Update #1 and included 7.1i IP Update #2, which includes the following:

- New Features in v2.1

- Bug Fixes in v2.1

- Known Issues in v2.1

NOTE: No updates or modifications were made to the Embedded Tri-mode Ethernet MAC Wrapper v2.1 Core as a result of 7.1i IP Update #2; thus, the information included below still applies to both 7.1i IP Update #1 and 7.1i IP Update #2.

For installation instructions and design tools requirements, see (Xilinx Answer 21019).

Solution

New Features in v2.1

- Added support for 1000BASE-X PCS/PMA mode.

- Added support for SGMII mode.

- Added UCF file example illustrating how to set the attributes for GT11 when using either the 1000BASE-X PCS/PMA or SGMII modes.

- Increased robustness of RGMII mode at 10/100 Mb/s by inserting an intermediate stage between rgmii_txc and the output DDR registers.

Bug Fixes in v2.1

CR 200967: Host interface is not enabled when DCR is selected.

CR 200333: IDELAY element should be added to RGMII_RXC clock instead of to RGMII_RXD and RGMII_RX_CTL signals when configuring the wrapper for RGMII mode.

CR 205836: RGMII TX clock should originate from CLIENTEMAC#TXGMIIMIICLKIN instead of EMAC#CLIENTTXGMIIMIICLKOUT.

Known Issues in v2.1

General Issues

- 1000BASE-X PCS/PMA or SGMII implementations error out in Synplify, indicating "port COMBUSIN does not exist." This is scheduled to be resolved in Synplify 8.1.

- The 16-bit interface option is currently not supported.

- The IOBDELAY_VALUE is not set correctly by BitGen in 7.1i, Service Pack 2. This affects designs that use the MII, GMII, or RGMII interfaces and results in IDELAY initializing incorrectly, possibly causing designs to fail on the board. To work around this issue, a BitGen patch must be installed on top of 7.1i, Service Pack 2. This will be resolved in 7.1i, Service Pack 3, at which time the patch will no longer be needed. For information on the patch, refer to (Xilinx Answer 21249).

- Dual RGMII EMAC configurations fail in MAP because the IDELAYCTRLs do not have LOC constraints. For more information on this issue and how to work around it, refer to (Xilinx Answer 21401).

- Designs that use the Virtex-4 EMAC (which have more than 8 BUFGs) fail to be placed in PAR. For more information on this issue, and details on how to work around it, refer to (Xilinx Answer 21402).

- The "Tx Enable" and "Rx Enable" options are disabled by default in the Embedded Tri-mode Ethernet MAC Wrapper CORE Generator GUI for both EMAC0 and EMAC1. If you do not enable this option during configuration of the wrapper, this might not allow the Embedded Tri-mode Ethernet MAC to be simulated (see Limitations of demo testbench below) or function in hardware until they are enabled. You can still enable the transmitter and/or receiver through the Host Interface or TIEEMAC#CONFIGVECTOR, if you do not want to regenerate the wrapper through CORE Generator.

- When using the Embedded Tri-mode Ethernet MAC Wrappers with configurations that use DCMs, new DCM timing parameters need to be considered which may require the use of the DCM_STANDBY macro. For more information, refer to (Xilinx Answer 21889).

Issues with gt11_dual_1000X.v(vhd) wrapper

- The CLK_COR_SEQ_1_2 attribute is incorrectly set for 1000BASE-X and SGMII interfaces in the gt11_dual_1000X file and ".ucf" file. For more information on this issue and how to work around it, refer to (Xilinx Answer 21403).

- The RXCLK0_FORCE_PMACLK and TXCLK0_FORCE_PMACLK attributes are incorrectly set to FALSE for 1000BASE-X and SGMII interfaces in the gt11_dual_1000X file and ".ucf" file. For more information on this issue and how to work around it, refer to (Xilinx Answer 21404).

Simulation issues

- VHDL Post-Translate, Post-MAP, and Post-PAR simulations do not work at 10/100 Mb/s with MII or GMII interfaces. For more information on this issue, refer to (Xilinx Answer 21563).

- Timing simulation does not work because the design fails to load during SDF annotation. For more information on this issue, refer to (Xilinx Answer 21600).

Limitations of demo testbench

- The demo testbench performs only full-duplex simulations, not half-duplex.

- The demo testbench does not simulate the DCR Interface (Host Type = DCR). Only simulations of the Host Interface (Host Type = Host) or no management interface (Host Type = None) are supported.

- If the wrappers are configured in tri-mode (10/100/1000 Mb/s), only 1 Gb/s rates are simulated. The demo testbench does not simulate all three speeds. In order to change the speed, you must use the Host Interface or DCR Interface and change the speed settings in the configuration registers.

- The "Tx Enable" and "Rx Enable" options are disabled by default in the Embedded Tri-mode Ethernet MAC Wrapper CORE Generator GUI for both EMAC0 and EMAC1. The demo testbench automatically enables them if configured with the wrappers Host Interface. However, if the Host Interface is not chosen, you must enable the transmitter and receiver by tying TIEEMAC#CONFIGVEC[57] = "1" and TIEEMAC#CONFIGVEC[50] = "1", respectively.

AR# 21049
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article