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AR# 21054

Virtex-4 RocketIO - 7.1.01i PAR does not place GT11's, GT11CLK's, BUFGs and MGTCLK pins correctly

Description

General Description:

When running PAR on a Virtex-4 design containing MGTs, PAR might error out due to unfeasible MGT nets routing.

Solution

For MGT resources to be placed and routed correctly, the MGT instance, the GT11CLK instance, and the MGTCLK input pads have to be explicitly LOC'd.

BUFG's connected to the MGTCLK pins have to also be explicitly LOC'd.

Example - 4Vfx60 FF1152 - Locking down the MGTCLK pins, MGT, and GT11CLK instances in a UCF file.

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#Begin Example UCF file - Please consult current Virtex4 MGT User Guide and Virtex4 data sheet for placement information

# Lock down the REFCLK pins:

NET "MGTCLKN_IN" LOC = "AP28" ;

NET "MGTCLKP_IN" LOC = "AP29" ;

# Lock down the MGT:

INST "INST_GT11" LOC = GT11_X0Y2;

# Lock down the GT11CLK

INST "INST_GT11CLK_MGT" LOC = GT11CLK_X0Y1;

#Lock down the BUFG

# Note that in all BUFG primitives, the location constraint is the same

# BUFG

INST "INST_BUFG" LOC = BUFGCTRL_X0Y1;

# BUFGCTRL

INST "INST_BUFGCTRL" LOC = BUFGCTRL_X0Y2;

# BUFGCE

INST "INST_BUFGCE" LOC = BUFGCTRL_X0Y3;

#End Example UCF file

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AR# 21054
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article