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AR# 21055

LogiCORE Ethernet Statistics v1.1 Core - Release Notes and Known Issues for the Ethernet Statistics Core

Description

General Description: 

This Answer Record contains the Release Notes for the LogiCORE Ethernet Statistics v1.1 Core, released in 7.1i IP Update #1 and included in 7.1i IP Update #2 and 7.1i IP Update #3, which includes the following: 

 

- New Features in v1.1 

- Bug Fixes in v1.1 

- Known Issues in v1.1 

 

NOTE: No updates or modifications were made to the Ethernet Statistics v1.1 Core as a result of 7.1i IP Update #2 or IP Update #3; thus, the information included below still applies to 7.1i IP Update #1, IP Update #2, and IP Update #3. 

 

For installation instructions and design tools requirements, see (Xilinx Answer 21019).

Solution

New Features in v1.1 

 

- N/A: First release of this core 

 

Bug Fixes in v1.1 

 

- N/A: First release of this core 

 

Known Issues v1.1 

 

1. Spartan-3E support has been reinstated for all speed grade devices because Spartan-3E -4 and -5 speed grade support has also been reinstated from the LogiCORE Gigabit Ethernet MAC and the LogiCORE Gigabit Ethernet MAC cores. See (Xilinx Answer 21043) and (Xilinx Answer 21044) for more information. 

 

2. Virtex-4 Verilog simulations in ModelSim PE cause memory collision errors. For more information on this issue, refer to (Xilinx Answer 21375)

 

3. Some transmitter statistics for the Virtex-4 Embedded Tri-mode Ethernet MAC do not increment. For more information on this issue, see (Xilinx Answer 21586). To resolve this issue, install the patch below and regenerate the core. 

 

4. The implementation script does not generate bitstreams for the Example Design if the target device is Spartan-3E. For more information, refer to (Xilinx Answer 21056)

 

Patch 

To resolve issue #3 from above, apply the following patch to the Xilinx ISE installation with 7.1i IP Update #1 or later: 

http://www.xilinx.com/txpatches/pub/swhelp/ip_updates/ethernet_statistics_v1_1_patch1.zip
http://www.xilinx.com/txpatches/pub/swhelp/ip_updates/ethernet_statistics_v1_1_patch1.tar.gz
http://www.xilinx.com/txpatches/pub/swhelp/ip_updates/ethernet_statistics_v1_1_patch1.gtar.gz
 

NOTE: If 7.1i IP Update #1 was installed followed by this patch and then 7.1i IP Update #2 or IP Update #3 was installed, the patch will need to be reinstalled because IP Update #2 and IP Update #3 will overwrite the existing patched files with the original incorrect ones. 

 

Install the patch as follows: 

1. Extract the contents of the ".zip", ".gtar,gz", or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.  

 

PC 

Determine the Xilinx installation directory by entering the following at the command prompt: 

"echo %XILINX%" 

 

UNIX or Linux 

Determine the Xilinx installation directory by typing the following: 

"echo $XILINX" 

 

NOTE: You might need to have system administrator privileges to install the patch.  

 

2. After installing the patch, regenerate the LogiCORE Ethernet Statistics v1.1 Core from CORE Generator. The core and supporting files produced will contain the fixes mentioned above.

AR# 21055
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article