Is there a minimum frequency requirement for RDClk?
For Virtex-4 series devices, when an SPI4.2 Core is used in Dynamic Phase Alignment (DPA) mode, there is a minimum frequency requirement of 220 MHz.
This requirement is needed because RDClk and RDat are source synchronous. RDClk sets the rate of RDat, which is crucial in performing data alignment. The edges on the RDat are needed to find the data-eye of incoming data (RDat). If RDat is running too slowly, a data transition might not be detected within 200-MHz period set by the ISERDES reference clock, and the DPA circuit will not be able to find the data-eye; therefore, the phase alignment cannot be completed.