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AR# 21089

7.1i XST - "ERROR:HDLCompilers:175 - Source file <>does not exist"

Description

Keywords: Verilog, include, core, CORE Generator

When I have COREGen cores in a different directory than the root project location, XST issues errors indicating that it cannot find the cores. When I set the "Verilog Include Directory", XST still cannot find them. I did not have this problem in 6.3i, but in 7.1i, the following errors occur:

"ERROR:HDLCompilers:175 - Source file mem1.v does not exist
ERROR:HDLCompilers:175 - Source file mem2.v does not exist
Analysis of file <"top.prj"> failed."

Solution

This problem occurs because the PRJ file is not written out correctly. Open the PRJ file ("top.prj" in this case) and note the incorrect locations to these Verilog files:

verilog work "mem1.v"
verilog work "mem2.v"

To solve this issue, change to the following correct locations:
verilog work "../IP/mem1.v"
verilog work "../IP/mem2.v"

You can also simply copy these files to the root project directory.

This problem has been fixed in the latest 7.1i Service Pack available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 3.
AR# 21089
Date Created 09/04/2007
Last Updated 01/07/2009
Status Archive
Type General Article