I cannot run applications out of SRAM using the plb_emc_v2_00_a Core. The memory test passes and I can read/write to the memory using XMD, but I cannot run a program from SRAM after loading it with XMD. I have tried this on both Virtex-4 and Virtex-II Pro boards, but I still cannot run a program out of SRAM.
The problem with running the code from SRAM has to do with some parameters not being set correctly on the plb_emc Core.
To run an application from SRAM via the plb_emc_v2_00_a Core, enable cacheline bursts; you can do this by setting C_INCLUDE_BURST_CACHELN_SUPPORT = 1 (default is 0).
Data width matching must also be enabled because the device you are interfacing to is 32-bits, and you are interfacing to it from the plb bus, which is 64-bits. To enable data width matching, set C_INCLUDE_DATAWIDTH_MATCHING_0 = 1.