We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 21147

Virtex-II Pro RocketIO - After deasserting RXRESET, why are RXDATA, RXCOMMADET and other RX signals "X" for a time?


In simulation, after deasserting RXRESET, it can be seen that the RXDATA, RXCOMMADET and other signals are "X" for a few clock cycles before resuming normal operation.


This usually occurs because the RXRESET is deasserted relatively soon after the RXP/RXN serial inputs stop being "X."

While the RX data path is in reset, its registers are held at 0, but when the reset is released, the data path receives data from the PMA. 

Because reset is released at a time when the serial inputs were so recently "X", a portion of the first two bytes out of the PMA are "X" 

This "X" condition propagates all the way through the RX data path until its appearance at the fabric.

This represents a latency of roughly 24 RXUSRCLK cycles, considering the latency through the elastic buffer (typically 18 cycles).

AR# 21147
Date 08/28/2017
Status Active
Type General Article
  • Virtex-II Pro