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AR# 21175

7.1i CORE Generator - ERROR:HDLCompilers:87- "<source_file>.v" line ## Could not find module/primitive '<IPcore_name>'

Description

Keywords: core, Verilog, VHDL, VHD, vhdl, vhd, translate, synthesis, analyse, analyze, compile, XST, xst, primary, secondary, unit, HDLParsers,3498

Urgency: Standard

General Description:
When running synthesis, I receive an error message similar to the following:

"ERROR:HDLCompilers:87 - designfile.v line 88 Could not find module/primitive 'my_core'"

It appears only when "Simulation Language = VHDL".

I might also see warning message(s) similar to the following:

"WARNING:HDLParsers:3498 - No primary, secondary unit in the file "c:\fpga_design\my_core.vhd. Ignore this file from project file "fpga_design.prj"."

Solution

These error messages and warning messages will be seen when a Verilog file instantiates an IP core (".xco" file) and the Simulation Language is set to VHDL.

When a VHDL file instantiates the ".xco", XST is able to get the needed pin information from the component declaration. However, when a Verilog file instantiates the ".xco" file, XST looks at the empty module file (".v" or ".vhd") of the instantiated core to get the needed pin information. In this latter case, if VHDL is the Simulation Language, the "<core_name>.vhd" file is sent to XST. There is no pin information available for the ".xco" file because the ".vhd" file appears to be empty for synthesis due to the placement of synopsys translate_off/on statements.

To work around this issue, do either of the following:

1. Use Verilog as the Simulation Language if possible.

2. Edit the "<core_name>.vhd" file and change the location of the synopsys translate_off/on statements so that synthesis sees the ieee lib declaration, the Entity declaration, the Architecture statement, the Begin, and the End.

Example ".vhd" file

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on

ENTITY my_core IS
port (
clk: IN std_logic;
sinit: IN std_logic;
din: IN std_logic_VECTOR(8 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(8 downto 0));
END fec_fifo_9;

ARCHITECTURE fec_fifo_9_a OF fec_fifo_9 IS
-- synopsys translate_off

component wrapped_fec_fifo_9
port (
clk: IN std_logic;
sinit: IN std_logic;
din: IN std_logic_VECTOR(8 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(8 downto 0));
end component;

-- Configuration specification
for all : wrapped_my_core use entity XilinxCoreLib.sync_fifo_v5_0(behavioral)
generic map(
c_read_data_width => 9,
c_has_wr_ack => 1,
c_dcount_width => 10,
c_has_wr_err => 0,
c_wr_err_low => 1,
c_wr_ack_low => 1,
c_enable_rlocs => 0,
c_has_dcount => 1,
c_rd_err_low => 1,
c_rd_ack_low => 1,
c_read_depth => 1024,
c_has_rd_ack => 1,
c_write_depth => 1024,
c_ports_differ => 0,
c_memory_type => 1,
c_write_data_width => 9,
c_has_rd_err => 0);

-- synopsys translate_on
BEGIN
-- synopsys translate_off

U0 : wrapped_my_core
port map (
clk => clk,
sinit => sinit,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout);

-- synopsys translate_on
END fec_fifo_9_a;


AR# 21175
Date Created 04/05/2005
Last Updated 12/13/2006
Status Archive
Type General Article