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AR# 21200

CPLD CoolRunner-II - How do I create a divided clock?


General Description:

How do I create both odd and evenly divided clocks in a CoolRunner-II?


For even numbered clock divisions, circuitry has been included in the CoolRunner-II CPLD architecture (128 Macrocell and larger) to divide one externally supplied global clock by standard values. Division by 2, 4, 6, 8, 10, 12, 14 and 16 are available. This capability is supplied on the GCK2 pin. The resulting clock produced will be 50% duty cycle for all possible divisions.

For odd numbered clock divisions, you still want to use the even numbered clock divider. Simply divide by twice the desired clock divisor, then take advantage of the dual edge flip-flops in the Macrocells. For example: If you wanted a divide by 3 clock, simply use a divide by 6 then configure the flip-flops in question to be dual edge, thereby converting that clock to a divide by 3.

For more information on the CoolRunner-II clocking resources, see the data sheet at:


AR# 21200
Date 01/30/2013
Status Active
Type General Article