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AR# 21207

PLB Ethernet v1_01_a - Latches are included in the design, MII Addressing Issue

Description


Urgency: Hot



General Description:

When I configure with DMA, the plb_ethernet v1_01_a contains latches. How can I fix this problem?



Additionally, the management interface falsely reports invalid PHYs.

Solution


The plb_ipif_v2_00_a and plb_ethernet_v1_01_a Cores have been updated to resolve the latch generation and invalid PHYs issue. It should be noted that EDK 7.1 is required to utilize this update.



The following steps detail the usage of the new cores:



1. Download both cores from the Xilinx FTP Site, and save the ZIP file in the <project_directory>\pcores directory:

http://www.xilinx.com/txpatches/pub/utilities/fpga/plb_ipif_v2_00_a.zip


http://www.xilinx.com/txpatches/pub/utilities/fpga/plb_ethernet_v1_01_a.zip


2. Unzip both cores into the pcores directory.



3. Close XPS.



4. Reopen XPS.



5. In XPS, select Tools -> Clean -> Netlist.



6. Select Tools -> Generate Netlist.



The new cores will no longer contain latches.
AR# 21207
Date Created 09/04/2007
Last Updated 03/24/2011
Status Archive
Type General Article