UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21239

7.1i UniSim, SimPrim, Simulation - block RAM (setup) memory collision violation on CLKA with respect to CLKB (address collision)

Description


General Description:

When I run an RTL simulation, the following types of errors occur for dual-port block RAM:



"Memory Collision Error on RAMB16_S36_S36:<instance_name> at simulation time <time> ns

A write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location <address> (hex) of Port A and address location <address> (hex) of Port B are unknown."



These violations occur when I write to an address on one port and read from that address on another port. This is a violation because the data that is read on the read port is not valid. In the hardware, the value that is read might be the old data, the new data, or a combination of old and new. In simulation, the output is "X" because the value that is read is unknown. For more information, refer to the Virtex-II User Guide at:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
Navigate to: FPGA Device Families -> Virtex-II -> Virtex-II Platform FPGA User Guide



From within the User Guide, go to Design Considerations -> Using Block SelectRAM Memory -> Synchronous Dual-Port and Single-Port RAM -> Conflict Resolution.

Solution


You should avoid collisions whenever possible. When an address is written to on one port, your design should not allow a read from the same address on the other port. However, this cannot be avoided in certain applications. As long as the value that is read on the second port is not used in your design, you can safely ignore the violations.



In ISE 7.1i, a new generic/parameter called SIM_COLLISION_CHECK has been introduced. The following strings can be used with SIM_COLLISION_CHECK



"ALL"

If there is a collision, write out collision messages as well as write Xs on the output.



"WARNING_ONLY"

If there is a collision, write only the message and do not write Xs on the output at the time of the collision.



"GENERATE_X_ONLY"

If there is a collision, generate Xs only on the output and do not write out a message.



"NONE"

If there is a collision, do not write out Xs on the output and do not write out the message.



The SIM_COLLISION_CHECK parameter/generic can be applied at an instance level. This enables you to change the setting for each block RAM Instance.



This is supported with all the Dual-Port RAMB16 iterations.



Refer to the ISE HDL Language Templates that are part of the ISE design tools for instantiation examples.
AR# 21239
Date Created 09/04/2007
Last Updated 05/04/2012
Status Archive
Type General Article