UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21271

7.1i Virtex-II PAR - Clock placer fails with invalid error

Description

Keywords: Bank, clock, placer, BUFGMUX

Urgency: Standard

General Description:
A case has been seen where the clock placer fails with incorrect errors related to BUFGMUX clock region conflicts. The problem is caused by incorrect correlation of IO banks to clock regions.

ERROR:Place:44 - The global clocks dram_clk_2_bufg_inst (BUFGMUX6P) and
core_clk_2x_180_bufg_inst (BUFGMUX6S) are locked into a primary / secondary
site pair. It is impossible to route all of the clock loads for both of
these clocks using the global clock routing resource. Only one of
primary/secondary pair clocks have access to any one region via global (high
drive/low delay/low skew) routing resources. If these two clocks drive clock
inputs in the same clock region, the nets will not be routable using the
global clock routing resources.
Please correct this before continuing. The following component are causing
the problems. One group needs to be removed out of the area.

WARNING:Place:498 - The Bufg Comp dram_clk_2_bufg_inst drives a locked component
in region 0, there is a BUFG->DCM Comp core_clk_2x_180_bufg_inst and
dram_clk_1_dcm_inst that exist in the same region placed by the clock placer.
As the two bufgs are placed in primary-secondary pair, this will cause phase 2
of clock placer to fail. Users should try to place their own dcms, or should
avoid locking comps in the 4 corner regions

WARNING:Place:498 - The Bufg Comp dram_clk_2_bufg_inst drives a locked component
in region 0, there is a BUFG->DCM Comp core_clk_2x_180_bufg_inst and
dram_clk_2_dcm_inst that exist in the same region placed by the clock placer.
As the two bufgs are placed in primary-secondary pair, this will cause phase 2
of clock placer to fail. Users should try to place their own dcms, or should
avoid locking comps in the 4 corner regions

WARNING:Place:498 - The Bufg Comp dram_clk_2_bufg_inst drives a locked component
in region 0, there is a BUFG->DCM Comp core_clk_2x_180_bufg_inst and
dram_clk_3_dcm_inst that exist in the same region placed by the clock placer.
As the two bufgs are placed in primary-secondary pair, this will cause phase 2
of clock placer to fail. Users should try to place their own dcms, or should
avoid locking comps in the 4 corner regions 3.2 (Checksum:1c9c37d) REAL time: 18 secs

Solution

This problem has been fixed in the latest 7.1i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 2.
AR# 21271
Date Created 09/04/2007
Last Updated 10/20/2008
Status Archive
Type General Article