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AR# 21274

Virtex-II Pro X RocketIO - What clock frequencies should I use when simulating 64B66B PMA_SPEED_MODEs?


General Description: 

What clock frequencies should I use when simulating 64B66B PMA_SPEED_MODES?


Due to simulator and HDL limitations, 64B66b PMA_SPEED_MODEs have to be simulated with exact frequencies; otherwise, you might see simulation discrepancies due to rounding errors. 


The USRCLK periods have to be 33/32 of the REFCLK frequencies. The resulting period is also dependant on the data width of the user interface. It will always be an integer multiple of the 33/32 ratio. 


Generally the PMA_SPEED_MODEs are set up to provide the right 33/32 ratio on the TXOUTCLK and RXRECCLK ports. 


For example: 


REFCLK = 3.2ns 

TXOUTCLK = RXRECCLK = USRCLK = 3.3ns (exact frequency multiple 3.2ns * 33/32 ) 



REFCLK = 1.6ns 

TXOUTCLK = RXRECCLK = USRCLK = 1.65ns (exact frequency multiple 1.6ns * 33/32 )

AR# 21274
Date 05/19/2014
Status Archive
Type General Article