When I run timing simulation using the design example, a DIP2 mismatch error occurs in the simulator. This error occurs only during timing simulation and is similar to the following error:
"# RStat Error: DIP2 error received. Expecting 11, received 10.
SnkDip2ErrReqFlag = 0. 4273233 ps
# ** Error: /var/tmp/xil_EAAOtaGr2(9475): $setup( posedge I &&& (in_clk_enable == 1):4594707 ps, posedge CLK:4594894 ps, 196 ps );"
This error is not a core issue, and is occurring because the relationship between RSClk and RStat is not consistent due to delay. The status monitor block routing of the demo testbench (pl4_status_monitor.v/vhd) does not compensate for this behavior, resulting in the demo testbench errors. Consequently, if the DIP2 mismatch error is originating from the demo testbench status monitor, you can safely ignore this error message.
This issue is fixed in the testbench delivered with SPI4.2 v8.3.