We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21317

Virtex-4 RocketIO - What are the wait cycles before DRDY is asserted in dynamic reconfiguration for the MGT?


NOTE: This Answer Record is specifically for the MGT. 

In the Virtex-4 FPGA Configuration User Guide v1.1 (Xilinx UG071), Chapter 6, Reconfiguration Techniques, Figures 6-4 and 6-5 on page 81 show an undetermined number of wait cycles from when DEN is asserted to when DRDY is asserted. 



For the MGT, the number of wait cycles after DEN is three (3) before DRDY is asserted.
AR# 21317
Date 05/19/2014
Status Archive
Type General Article
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • More
  • Virtex-4 SX
  • Virtex-4Q
  • Virtex-4QV
  • Less
Page Bookmarked