We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21325

LogiCORE Tri-mode Ethernet MAC v2.1 Core - IO standard constraints for RGMII interface are incorrect


General Description:

The user guide for the Tri-mode Ethernet MAC v2.1 Core references that the RGMII interface is designed according to the RGMII v2.0 spec. The RGMII v2.0 spec states that HSTL should be used as the I/O standard for the RGMII interface. However, both the constraints section of the user guide and the example ".ucf" file provided with the core use 3.3 LVTTL. Which one is correct and which one should I use?


The RGMII interface is logically designed according to the RGMII v2.0 spec. Consequently is should use HSTL as the I/O standard. This will be fixed in a future revision of the core.

To work around this issue, change the I/O standard of the RGMII signals to HSTL.

Although the RGMII interface is logically designed to the RGMII v2.0 spec, the design is implemented entirely in the example design. Therefore, if the RGMII v1.2 interface is required, the design could be modified accordingly. The receiver for both versions are logically identical. The transmitter logic for v2.0 forwards the clock in the center of the data valid window (the clock is driven from CLK90, the data from CLK0) while the transmitter logic for v1.2 forwards the clock in sync with the data and relies on a longer trace length of the clock on the PCB to create the clock-to-data skew (therefore both clock and data are driven from CLK0).

Also, you should always check the PHY data sheet to see what I/O standard and RGMII version it expects for its RGMII interface.

AR# 21325
Date 12/15/2012
Status Active
Type General Article