UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21329

NC-Verilog, 7.1i - When doing a simulation of block RAMs, I discover that there are compilation errors in the Verilog BlockRam Models in software older than IUS53

Description

General Description: 

When doing a simulation of block RAMs, I discover that there are compilation errors in the Verilog BlockRam Models in software older than IUS53.

Solution

Starting in ISE 7.1i, all the blockRam models have been re-coded to use 2-D Arrays. In order to achieve this in Verilog, advanced Verilog-2001 constructs had to be used. Cadence's NCSIM software only supports these advanced constructs in the IUS software suite. It is highly recommended to upgrade to the IUS software with ISE 7.1i, as this is the Xilinx tested version. 

 

To work around this issue, you can use the following switches: 

 

- command line: ncvlog -DEFINE legacy_model 

- command line: ncverilog +define+legacy_model 

 

This will compile the non-2D array models for the block RAM, and the simulation will continue.

AR# 21329
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article