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AR# 21334

6.3 EDK - PlatGen - Verilog `include compile directive in pcore not supported

Description

Keywords: EDK, Verilog, Platgen, pcore, user IP, path

Urgency: Standard

General Description:

Currently, a Verilog `include (using a relative path) is not possible within the HDL of a pcore.
For instance,

module mycore(...);
....
`include "mybram_inits.v"
....
endmodule

This results in a platgen error as the included file can not be found.

The problem is that Verilog tools search the *run* directory for the `include
file, then directories specified as Verilog include directories. Tools do not
look in the directory of the file with the `include.

Solution

This problem has been fixed in the latest EDK 7.1i Service Pack available at:
<http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp>
The first service pack containing the fix is EDK 7.1i Service Pack 1.
AR# 21334
Date Created 04/27/2005
Last Updated 04/12/2007
Status Archive
Type General Article