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AR# 21340

LogiCORE SPI-4.2 (POS-PHY L4) v7.2 - CORE Generator errors when SnkAFThresAssert <6 is selected

Description

General Description: 

When I set sink or source Almost Full Assert values (SnkAFThresAssert or SrcAFThresAssert) to less than 6, CORE Generator displays errors during generation. 

 

The following errors occur in the CORE Generator console: 

 

"ERROR:coreutil - Parameter c_snk_af_thres_assert value 5 is outside the range 6 to 508." 

"ERROR:coreutil - Failure to set parameters on core: Error Setting Sim Parameters" 

"ERROR:coreutil - Failure to generate output products"

Solution

For the Sink or Source FIFO Threshold setting, if you select Almost Full Assert to be less than 6, the GUI will not flag that you have set an incorrect value. However, when you generate the core, it will fail and notify you that the value is out of range. This is an issue related to the CORE Generator GUI. 

 

For SPI-4.2 v7.2, the valid ranges for FIFO Threshold setting are: 

Sink Core  

Almost Full Assert (SnkAFThresAssert): 1 to 508 

Almost Full Negate (SnkAFThresNegate): SnkAFThresAssert to 508 

 

Source Core (if SrcBurstMode = 0):  

Almost Full Assert (SrcAFThresAssert) : 1 to 508  

Almost Full Negate (SrcAFThresNegate): SnkAFThresAssert to 508 

 

Source Core (if SrcBurstMode = 1):  

Almost Full Assert (SrcAFThresAssert) : SrcBurstLen to 508 

Almost Full Negate (SrcAFThresNegate): SrcAFThresAssert to 508  

 

To work around this issue, enter the threshold values greater than 6 for Almost Full Assert on both the sink and source, and generate the core. Then, using a file editor, open the top wrapper file:  

 

... /example_design/<component_name>_top.v 

 

or ".vhd" file and change the static configuration values to your desired setting. 

 

The section of the file you will need to edit is found below: 

 

//**************************************************************************** 

// The following signal instantiations are the Static Configuration signals. 

//**************************************************************************** 

assign LoopbackEn_n = 1'b0; 

assign NumDip4Errors = 4 ; 

assign NumTrainSequences = 4 ; 

assign NumDip2Errors = 4 ; 

assign NumDip2Matches = 4 ; 

assign SnkAFThresAssert = 32 ; <===  

assign SnkAFThresNegate = 32 ; <===  

assign SrcAFThresAssert = 32 ; <=== 

assign SrcAFThresNegate = 32 ; <=== 

 

This issue has been fixed in the SPI-4.2 v7.3 Core delivered with 7.1i IP Update #3. Xilinx recommends that you upgrade to the latest core.

AR# 21340
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article