On Virtex-4 designs using 7.1i SP2 or earlier, the IOBDELAY_VALUE is not set correctly by BitGen. This results in IDELAY initializing incorrectly, which causes PCI designs to fail on the board. These designs do work in timing simulation.
You should update to 7.1i SP3 or later since 7.1i SP3 and later solves this problem.
If you need to use 7.1i SP2, you must download a BitGen patch that should be installed on top of 7.1i SP2. For information on the patch, refer to (Xilinx Answer 21249).