Figure 5 on page 11 of the "On-Chip Peripheral Bus IP Interface Packet FIFO", ( DS415 (v1.4) January 13, 2003 ) shows a latency of 2 clock cycles between Write-Request going active and Write-Ack going active. However, in simulation, a 3 clock cycle latency is seen. Which is correct?
There is a discrepancy in the data sheet. The latency between the Write-Request going active and Write-Ack going active is 3 clock cycles (not 2).