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AR# 21429

OPB IPIF v2.00h - The latency between Write-Request and Write-Ack is incorrect in the data sheet

Description

General Description: 

Figure 5 on page 11 of the "On-Chip Peripheral Bus IP Interface Packet FIFO", ( DS415 (v1.4) January 13, 2003 ) shows a latency of 2 clock cycles between Write-Request going active and Write-Ack going active. However, in simulation, a 3 clock cycle latency is seen. Which is correct?

Solution

There is a discrepancy in the data sheet. The latency between the Write-Request going active and Write-Ack going active is 3 clock cycles (not 2).

AR# 21429
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article