How long do the various JTAG instructions take to execute:
Users programming 9500 devices with a micro processor have
wanted to know how long to wait for different jtag instructions
to complete execution.
1. Are these operations self-timed?
2. How long does his processor have to wait between cycles?
3. What is the range of delay From the shortest time to the
longest time? Is there a maximum period?
Each operation has a shifting time associated with shifting in
the bits of the instruction and the associated data. This time
is dependent on the method used to access the TAP. The maximum
TAP speed of the xc9500 is typically 10MHz.
The speed at which you operate your boundary-scan chain will be
determined by the slowest part on the chain.
The instruction register length for the xc9500 is 8 bits and
the data length varies as per the instruction. The differing
data register sizes can be extracted from the device BSDL
files. They range from 1 bit (the BYPASS register) to several
hundred bits (the BOUNDARY-SCAN register) in length.
The programming (FPGM, FPGMI) and erase (FERASE, FBULK)
instructions also have a "Flash" or "latency" time associated
with them. This is time to be spent in the Run-Test/Idle state
while waiting for the operation to actually complete.
For program this time is typically 160 usec.
For erase this time is typically 1.3 seconds.
These flash operations are self-timed and require no pulsing of
TCK (although TCK can pulse). The operations shut off
automatically if you wait longer than the required time.
Leaving Run-Test/Idle prematurely terminates the operation in
There is no minimum or maximum range specified. The times are
set at the factory to guarantee completion of the specified
Please note all these flash times are encoded in the SVF file
into the part are included in the SVF file in the correct order
to effect the required operations.