We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 21441

LogiCORE SPI-4.2 (POS-PHY L4) v7.2 - MAP: "WARNING:LIT:381 - Attribute FACTORY_JF should be set to F0F0 for DCM_ADV symbol "pl4_src_clk0/tsclk_dcm0"


Regardless of DLL Frequency Mode (High or Low), the DCM_ADV should have the attribute FACTORY_JF set to "F0F0". If the FACTORY_JF is not specified when instantiating the DCM_ADV in Verilog for the Virtex-4 devices, Xilinx Synthesis Tool (XST) will set "C080" as the default instead of the correct value of "F0F0." This could potentially cause problems on the board.

In the SPI4.2 design, when using the master clocking mode, all the DCMs used in the design have the appropriate FACTORY_JF settings; however, when using the slave clocking mode, the clocking module provided in the design example (pl4_src_clk.v) does not have the FACTORY_JF specified for tsclk_dcm0 and tdclk_dcm0.

To work around this issue, specify the correct attribute value (FACTORY_JF = 'F0F0") in the code (pl4_src_clk.v).
Please see Virtex-4 User Guide for more information on FACTORY_JF setting.

AR# 21441
Date 05/03/2010
Status Archive
Type General Article