We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21448

Schematic - "ERROR:DesignEntry:239 - Incorrect bus tap at (x,y,x,y); destination branch 'd-branch-name' is not part of the source branch 's-branch-name'"


When I run a process on a schematic design module, the following error occurs:

"Started process "View HDL Functional Model".

ERROR:DesignEntry:239 - Incorrect bus tap at (x,y,x,y); destination branch 'd-branch-name' is not part of the source branch 's-branch-name'."

In ISE 6.xi, the error message was:

"ERROR:DesignEntry:100 - Destination branch of bus tap at (x,y,x,y) is not part of the source branch of the bus tap."


Before a schematic design is implemented, it is first converted to either Verilog or VHDL (depending on the setting of the Generated Simulation Language property). As part of the conversion process, a Design Rule Check (DRC) will be run on the selected schematic and any underlying schematics. "Error: DesignEntry:239" indicates that the a bus tap connects to nets with different base names.

A bus tap is a visual representation of the association of the main bus (source) and a scalar net or sub bus (destination branch) that is taken from it. In reality, it is the name of the branches that determines the electrical connection. For example, a branch named "data(1:0)" will be electrically connected to the two LSBs of a bus branch named "data(3:0)."

The electrical connection is made regardless of whether the two branches are physically connected with a bus tap in the schematic drawing. Since the bus tap is just a visual representation, the error message is generated if the representation is inaccurate (the source and destination do not have the same base name).

AR# 21448
Date 12/15/2012
Status Active
Type General Article