The PCI Express 32-bit PIPE Core Data Sheet (DS321 April 11, 2005) says the following regarding the system clock input signal:
The system clock signal is required only for certain designs. Where required, the system clock is used to clock logic that coordinates the hardware reset process. This clock must be a free-running clock between 10 MHz and 100 MHz that is not a DCM output. It is important to clarify that this clock is not related to the reference clocks used or generated by the external PHY.
What does it mean by saying The system clock signal is required only for certain designs?
Also, Table 2 states that the clock should be 125 MHz.
This is misleading and will be changed, along with Table 2, in the next version of the data sheet. The PIPE Core design requires a free-running non-DCM output system clock between 10 and 100 MHz. The range is large so users who already have a clock available can use it for this purpose.