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AR# 2150

CPLD XC9500 - The high-level output voltage of an XC9500 CPLD is ~4 volts


General Description:

The XC9500 uses two N-type transistors in the totem-pole of an output driver. This allows the driver to be much faster and smaller than if a P-type transistor is used for the pull-up. One drawback of this approach is that the N-type transistor drops 1.0-1.2V and the high-level output voltage is approximately 4V. This is not a problem with standard TTL and CMOS logic because the required VIH for these families is 2.0V and 3.0V, respectively. However, some CMOS device families require Vih to be 4.0 V or greater.

Is there any way to increase the XC9500 high output voltage level?


You cannot set any switches to change the configuration of the XC9500 output drivers to CMOS, however, you can perform the following external to the chip:

1. Set VCCIO to 5.5V, which is the absolute max.

a) Check the LIH (leakage current) of the CMOS devices that are being driven.

b) Multiply it with the number of the CMOS I/O to be driven.

c) If the total leakage current does not exceed 4 mA, and VCCIO is at 5.5V, the outputs should give a Voh of about 4.5V.

2. Use buffers between pins that need extra drive.

AR# 2150
Date 12/15/2012
Status Active
Type General Article