We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 21563

Embedded Tri-mode Ethernet MAC Wrapper v2.1 - VHDL Post-Translate, Post-MAP, and Post-PAR simulations do not work at 10/100 Mb/s with MII or GMII interfaces


General Description:

VHDL SimPrim simulations of the Virtex-4 Tri-mode Ethernet MAC that use the PHYEMAC#MIITXCLK clock, which include the MII interface operating at 10/100 Mb/s and the GMII interface operating in tri-speed mode, do not work. The symptom is that the core does not respond or pass any frames through even though all of the inputs are correct.

Behavioral simulation is okay since it uses UniSim models instead of SimPrims. Only Post-Translate, Post-MAP, and Post-PAR simulations are affected.


An issue exists with the VHDL SimPrim SmartModel (simprim_SMODEL_mti.vhd) for the EMAC in which PHYEMAC#MIITXCLK signal is not getting passed into the SmartModel. Consequently, the logic being clocked by this signal is not functioning, which causes the core to not function in simulation.

This issue will be resolved in ISE 7.1i Service Pack 4.

AR# 21563
Date 12/15/2012
Status Active
Type General Article