VHDL SimPrim simulations of the Virtex-4 Tri-mode Ethernet MAC that use the PHYEMAC#MIITXCLK clock, which include the MII interface operating at 10/100 Mb/s and the GMII interface operating in tri-speed mode, do not work. The symptom is that the core does not respond or pass any frames through even though all of the inputs are correct.
Behavioral simulation is okay since it uses UniSim models instead of SimPrims. Only Post-Translate, Post-MAP, and Post-PAR simulations are affected.
An issue exists with the VHDL SimPrim SmartModel (simprim_SMODEL_mti.vhd) for the EMAC in which PHYEMAC#MIITXCLK signal is not getting passed into the SmartModel. Consequently, the logic being clocked by this signal is not functioning, which causes the core to not function in simulation.
This issue will be resolved in ISE 7.1i Service Pack 4.