The XST tool in 7.1 EDK and higher is using one additional BUFG than the 6.3 release did. This is causing my design to not fit with the new software release.
To work around this issue, follow these instructions:
To eliminate this additional BUFG, add the following lines/attribute to the "spi_module.vhd" located in the "<edk>\hw\XilinxProcessorIPLib\pcores\opb_spi_v1_00_c\hdl\vhdl" directory.
attribute buffer_type : string;
attribute buffer_type of SCK_SR_local : signal is "none";
After adding these attributes, clean and re-generate your project design.
The above solution will work with other Processor IPs, if you apply the attribute to the correct signals in the HDL code