You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
7.1i NetGen, Timing Simulation Virtex-4 - The OSERDES component does not have a clock to out that matches the ODDR component
Keywords: simulate, SimPrim, x_oserdes, oserdes, delay, output, timing, x_oddr
During a timing simulation, there is a clock to out delay discrepancy between output of an OSERDES when compared to an ODDR. Since the ODDR is a subset of the OSERDES, this delay should match.
This issue is a result of the simulation model not responding to the IOPATH delay on the component.
This issue will be fixed in ISE 8.1i Service Pack 3.
Was this Answer Record helpful?