DCM CLKFX sometimes outputs a clock pulse that does not have the correct period. What could be causing these unwanted periods?
The CLKFX outputs can potentially have abrupt period shifts if the CLKIN inputs have excessive jitter. These shifts might occur at every clock "concurrence." Clock "concurrences" are the times when the rising edges of the input clock and the output clock are (or should be) in phase. It occurs every D cycles of CLKIN, and every M cycles of CLKFX.
The following diagram provides an example of when CLKFX is used with M=7 and D=5:
The DCM DFS circuit (which creates the CLKFX output) has logic to determine every clock concurrence. At each concurrence, the CLKIN rising edge is automatically transferred onto the CLKFX rising edge. This is how CLKFX keeps the phase relationship with CLKIN. Thus, if the CLKIN input has excessive jitter, CLKFX output will match the phase of that jittery clock at every concurrence. This could result in a sudden increase/decrease in the output pulse, as shown in the example below:
It is always good design practice to monitor the STATUS output signals out of the DCM. If STATUS goes high, indicating the CLKFX output has stopped, a RESET of the DCM is required. If the LOCK output goes low, indicating the DCM has lost its frequency or phase alignment and calibration to the input clock, then a RESET of the DCM is required. In these cases, a RESET will allow the DCM to obtain LOCK on the input clock and resume normal operation.
Please refer to (Xilinx Answer 19827) for more information on DCM jitter.