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AR# 21604

7.1i UniSims - FDDRRSE/FDDRCPE simulation model is not working properly due to delta delays


Keywords: UniSim, FDDRRSE,FDDRCPE, delta delay, output, incorrect, clock

In ISE 7.1i, the FDDRRSE and FDDRCPE have been updated, and this can cause delta delay problems. These delta delay problems result in the input data being registered out on the same clock edge as it was registered in. This causes the output to be available one clock cycle early.


To work around this problem, you can add a delay to the data input to the FDDRRSE or FDDRCPE in the testbench.

This issue is fixed in the ISE 8.1i design tools.
AR# 21604
Date 10/16/2008
Status Archive
Type General Article
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