When implementing a SPI4.2 Lite Core design targeting a Virtex-II device using ISE7.1i, you might receive a timing error such as the following:
"Timing constraint: OFFSET = IN -0.77 ns VALID 2.2 ns BEFORE COMP "RDClk_P" TIMEGRP RD_DDR_R;
32 items analyzed, 32 timing errors detected. (0 setup errors, 32 hold errors)
Offset is -2.892ns."
To work around this failure, manually change the RDClk DCM phase shift value in the UCF file from 62 to 32.
1. Using the file editor, open the appropriate constraint file located in:
2. Look for a line with:
INST "pl4_lite_snk_top0/pl4_snk_clk0/rdclk_dcm0" PHASE_SHIFT = 62;
3. Change the phase shift value from "62" to 32".
4. Save and Close the file.
5. Re-run the implementation.