I have a pass-thru symbol in my design and the following warning messages appear in the MAP report:
"WARNING:MapLib:328 - Block inst_2459/inst_36 is not a recognized logical block.
The mapper will continue to process the design but there may be design
problems if this block does not get trimmed."
"WARNING:PhysDesignRules:367 - The signal <inst_2459/wire_net_4_155<24>> is
incomplete. The signal does not drive any load pins in the design."
When I examine the design in FPGA Editor, the connection defined by the pass-thru symbol is broken. Why does this occur?
The pass-thru symbol is a hierarchical symbol that contains only wire connections from pin to pin, and no lower-level symbols. The physical implementation of this symbol is incorrect when it is preserved by KEEP HIERARCHY constraints, but the connectivity defined is handled correctly when KEEP HIERARCHY is turned off for the pass-thru symbol. This can be done either globally with the "-ignore_keep_hierarchy" MAP switch, or it can be done specifically using UCF constraints with the symbol names from the warning messages:
INST "inst_2459/inst_36" KEEP_HIERARCHY = FALSE ;
Note also that wildcards can be used in the UCF constraints, for example:
INST "inst_2459/inst_*" KEEP_HIERARCHY = FALSE ;
This problem is scheduled to be fixed in version 10.1i.