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AR# 21629

System Generator for DSP and XtremeDSP Development Kit - When using the QAM example provided with System Generator for DSP, "ERROR:MapLib:30 - LOC constraint F7 on dac2_d(13) is invalid: N" occurs

Description

Why do I receive an invalid constraint error message when using the supplied QAM example with the Xtreme DSP Development KIT-II (2v3000)?

The System Generator for DSP QAM example is located in "$\FUSE\XtremeDSP Development Kit-II\Examples\system_generator_examples\QAM".

The "sysgenqam16_dplr.mdl" DAC1 and DAC 2 constraints are not correct for the Xtreme DSP Development KIT-II with 2V3000; they are for the XtremeDSP Development Kit with the 2V2000.

Solution

The XtremeDSP Development Kit-II 2V3000 UCF is located at:

$\FUSE\XtremeDSP Development Kit-II\UCFs

The UCF shows how the 2V80 and the 2V3000 pins connect to the on-board components.

Update the "sysgenqam16_dplr.mdl" DAC FPGA pins as shown below:

################

## DAC Signals

################

#DAC Channel 1

#NET DAC1_D<0> LOC = V24 ;

#NET DAC1_D<1> LOC = U24 ;

#NET DAC1_D<2> LOC = U23 ;

#NET DAC1_D<3> LOC = U22 ;

#NET DAC1_D<4> LOC = U21 ;

#NET DAC1_D<5> LOC = T19 ;

#NET DAC1_D<6> LOC = R24 ;

#NET DAC1_D<7> LOC = R23 ;

#NET DAC1_D<8> LOC = R19 ;

#NET DAC1_D<9> LOC = P23 ;

#NET DAC1_D<10> LOC = P22 ;

#NET DAC1_D<11> LOC = P21 ;

#NET DAC1_D<12> LOC = P20 ;

#NET DAC1_D<13> LOC = P19 ;

#NET DAC1_DIV0 LOC = T20 ;

#NET DAC1_DIV1 LOC = T24 ;

#NET DAC1_MOD0 LOC = R21 ;

#NET DAC1_MOD1 LOC = R22 ;

#NET DAC1_PLLLOCK LOC = R20 ;

#NET DAC1_RESET LOC = V23 ;

#DAC Channel 2

#NET DAC2_D<0> LOC = AD21 ;

#NET DAC2_D<1> LOC = AC21 ;

#NET DAC2_D<2> LOC = AB24 ;

#NET DAC2_D<3> LOC = AB23 ;

#NET DAC2_D<4> LOC = AB20 ;

#NET DAC2_D<5> LOC = AB19 ;

#Note that two pins are provided here as on the actual PCB due to the need to provide support for multiple devices. Either pin can be used but not both at once.

#NET DAC2_D<5> LOC = AB18 ;

#NET DAC2_D<6> LOC = AA24 ;

#NET DAC2_D<7> LOC = AA23 ;

#NET DAC2_D<8> LOC = AA22 ;

#NET DAC2_D<9> LOC = AA20 ;

#NET DAC2_D<10> LOC = AA19 ;

#NET DAC2_D<11> LOC = Y22 ;

#NET DAC2_D<12> LOC = Y20 ;

#NET DAC2_D<13> LOC = Y19 ;

#NET DAC2_DIV0 LOC = AC17 ;

#NET DAC2_DIV1 LOC = AD17 ;

#NET DAC2_MOD0 LOC = T22 ;

#NET DAC2_MOD1 LOC = T21 ;

#NET DAC2_PLLLOCK LOC = AB16 ;

#NET DAC2_RESET LOC = U20 ;

AR# 21629
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article