AR# 21632

How do I integrate per pin parasitic package data (in the .pkg file) provided in the IBIS archive into the IBIS file? How do I ensure that the latest IBIS model and package models are adopted by write_ibis/IBISWriter when generating custom IBIS file?


Xilinx provides IBIS models in two ways: generic family spanning models (direct from the Web), through the IBISWriter program (available as part of the ISE design environment) and most recently using the write_ibis command in Vivado.

IBISWriter is a utility which takes in a design implementation (.ncd) file, and outputs a custom IBIS file specific to the design.

Vivado write_ibis takes a synthesized or implemented netlist (or DCP) and creates the custom IBIS model for the design.

Xilinx IBIS models contain two types of information:

  1. I/O models describing the analog behavior of a pin depending on its I/O standard.
  2. Package models describing either coarse package min, typ, max delay or (if available) detailed package parasitics models (see .pkg files) which in addition to per pin die pad to package ball delay, also allow simulation of package crosstalk.


There are several methods for including package parasitic data and each has their own benefits.

To account for package parasitic data in your IBIS simulation, you can use one of the following options:

Manually inserting .pkg information in a generic IBIS model (Option 1) is the most efficient option when you want to use multiple specific pins, but do not have an NCD file or a DCP that contains design information.

Using IBISWRITER or Vivado write_ibis (Option 2) is the easiest method of the three and is the most efficient option when you have an NCD or Vivado netlist created with the IOSTANDARDs and pin locations set for the design.

Option 3 is a manual method for simply editing the generic IBIS model when you want to quickly simulate a pin with specific non-coupled pin parasitic data.

Option 1: When using the generic IBIS file:

a) The family base generic IBIS file can be found in the Xilinx download center.

b) Per pin package parasitic data (if available) for the device family is included with the IBIS archive downloaded from the Xilinx download center. 

Each .pkg file represents a die/package combination within the family. Package naming convention: <PackageName_DieName_ibis>.pkg . 

If needed, please contact Xilinx technical support for assistance in acquiring the .pkg files for your target device and package.

i) If this is not available:

  1. Use the coarse package parasitic provided in the family IBIS file (<family>.ibs).
  2. Find the package of interest and uncomment the data R_pkg, C_pkg, and L_pkg identifiers.
  3. Comment all other packages (comment character in IBIS is "|").
  4. Simulate.

ii) If available, it is easiest to use the IBISWriter utility in ISE or write_ibis command in Vivado. 

If IBISWriter or the write_ibis command do not incorporate the package parasitic data into the IBIS you can manually edit the IBIS with the data from the .pkg file. Reference steps can be found below.

1) In the [pin] section, edit and ensure every generic pin in the device/package is defined and assigned a net name and model name. An example of an edit pin section portion is shown below.

[Pin] signal_name model_name






2) Look for lines with the [Define Package Model] and [End Package Model] keywords in the .pkg file of interest.

3) Insert these two lines and everything in between immediately before the last line (line with IBIS keyword [End]) of the IBIS file.

4) Immediately above the first occurrence of [Model] line, type in: [Package Model] <pkg_model_name>. 

The <pkg_model_name> is available next to the [Define Package Model] line copied in the previous step. Make sure the <pkg_model_name>s for these two lines match.

[Package Model] ffg900_xc7k325t

//Model section

[Model] LVDS_HP_I

//model parameters

[Model] DIFF_SSTL135_T_DCI

//model parameters


[Define Package Model] ffg900_xc7k325t

5) Simulate.

Option 2: When using the custom IBIS file (IBISWriter utility):

a) A design specific custom IBIS file is generated from IBISWriter (available as part of the ISE design environment), IBISWriter takes in a design implementation (.ncd) file, and IBISWriter outputs a custom/design specific IBIS file ready for simulation.

b) Per pin package parasitic data (if available) can be included in the custom IBIS file.

i) From the Command line: use the -pin option or manually insert into the custom IBIS file as described in paragraph 1.b.ii above.

ii) Within the ISE GUI:

In the Processes window:

  1. Expand the Implement design tree.
  2. Expand the Place and Route tree.
  3. Right-click Generate IBIS Model and select Properties.
  4. Enable checkbox Generate Detailed Package Parasitics.
  5. Double-click Generate IBIS Model to create to output file.

c) To ensure the custom/design specific IBIS file contains the latest I/O model and package parasitic data:

i) For Virtex-4 and Virtex-5, run XilinxUpdate prior to the launch of IBISWriter. XilinxUpdate can synchronize the data file under the ISE database with the latest IBIS data available in the Xilinx download center.

ii) For other devices, if the IBIS data in the Xilinx download center is updated after an ISE release, then the IBISWriter utility cannot be used and you must configure the I/O model and package model manually with the steps below:

  1. Download the latest available IBIS model from the download center.
  2. Manual update of the I/O model:
    -- For all models used in your design, look for the [Model] keyword, and copy everything until the next [Model] keyword.
    -- Annotate the pin list to link each I/O pin using the new I/O model: Look for the [Pin] keyword. For all I/Os in your design if it is not already listed, then add a reference to it here; if it is already listed, verify that it references the appropriate model.
    In this section, there should be one line per package pin. Syntax is: < pin number > < user-supplied pin name > < model name as defined by the [Model] keyword >.
  3. Manual updates of the package model:
    -- Process is described in paragraph 1.b above.

Option 2: When using the Vivado write_ibis:

a) You can open the synthesized or implemented design netlist or you can use Vivado to open a design checkpoint (DCP)

b) You can use write_ibis from the Tcl console or in the GUI.

  1. From the console the syntax is write_ibis -file your_file_name.ibs. This will select the installed ibis model and package file. You can override this with a different generic IBIS model using the -ibs switch and the -pin option to specify your own PKG file to annotate to the model.
  2. From the GUI you need to select File > Export > IBIS model. This will bring up the write_ibis window. From there you can override the default IBIS model and PKG file if needed.

Option 3: If you are just simulating want quick pin specific data but do not have an .ncd file, you can simply edit the generic package information with non-coupled pin specific details taken from the .pkg file.

The example below uses HSTL_I on pin A2 of a Spartan-6 LX16 CS324. 

Open the file called cs324_6slx16_ibis.pkg inside the file available on 

Lines 359 and 360 are as follows:

[Row] A2

This means that R_pin is 0.187482 for that pin.

Lines 855 and 856 are as follows:

[Row] A2
A2 7.34996e-009

This means that the L_pin is 7.34996e-009

Lines 1351 and 1352 are as follows:

[Row] A2
A2 1.07694e-012

This means that C_pin is 1.07694e-012.

Let's say their Vccaux is 2.5V. Pin A2 is in Bank0, which is the Top bank. 

This means that they would be using the HSTL_I_TB_25 model in their simulations. 

In the spartan6_v1p5_prelim_110822.ibs file, that model is associated with the pin number in the [Pin] section of 155.

You would need to change line #425 for pin 155 as follows:

From this:

155 HSTL_I_TB_25 HSTL_I_TB_25

Change it to this:

155 HSTL_I_TB_25 HSTL_I_TB_25 0.187482 7.34996nH 1.07694pF

Now the simulator will be using the per-pin RLC information (it overrides the R_pkg, L_pkg, C_pkg) for that pin.

AR# 21632
Date 03/20/2017
Status Active
Type General Article
Devices More Less