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AR# 21661

LogiCORE Pipelined Divider v3.0 - I can not do the behavior simulation if the optional pins are not available (CE, ACLR, SCLR)

Description

Keywords: CoreGen, 7.1i, Pipelined, Divider, v3.0, extra, signals, CORE Generator, VSIM, template, VEO, behavior, simulation, model, ce, aclr, sclr

Urgency: Standard

Description:

In the Pipelined Divider v3.0 core in Core Generator 7.1i there are optional pins available (CE, ACLR, SCLR).
When these optional signals are left unselected, the customer can not do the behavior simulation.
The behavior simulation model generated by the CoreGen is not correct.

# ** Error: (vcom-1130) Formal port "aclr" declared in entity "sdivider_v3_0" is not in the component declaration being instantiated.
# ** Error: (vcom-1130) Formal port "sclr" declared in entity "sdivider_v3_0" is not in the component declaration being instantiated.
# ** Error: (vcom-1130) Formal port "ce" declared in entity "sdivider_v3_0" is not in the component declaration being instantiated.
# ** Error: VHDL Compiler exiting
# ** Error: %Modeltech%/win32/vcom failed.

Solution

1. It will be fixed in the new version (v3.1) Pipelined Divider.
2. Please use post-translate simulation as the workaround.
3. If the customer have to do the behavior simulation, he should choose the three pins and connect them to the value.

AR# 21661
Date Created 09/04/2007
Last Updated 03/02/2008
Status Archive
Type General Article