We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21665

LogiCORE Fibre Channel v2.0 Core - Simulation fails in 7.1i Service Pack 3 because RX_LOS_INVALID_INCR and RX_LOS_THRESHOLD signals are missing from SmartModel


General Description: 

Simulations of the LogiCORE Fibre Channel v2.0 Core, that are targeted to Virtex-4 FX devices, fail to load during simulation in 7.1i Service Pack 3 that previously worked in 7.1i Service Pack 2. Specifically, both Verilog and VHDL simulations fail with errors similar to the following with respect to RX_LOS_INVALID_INCR and RX_LOS_THRESHOLD signals: 


# ** Error: (vsim-3043) ../../example_design/transceiver.v(969): Unresolved reference to 'RX_LOS_INVALID_INCR' in GT11_1XFC_2_INST.RX_LOS_INVALID_INCR. 

 # Region: /testbench/DUT/transceivers_i 

 # ** Error: (vsim-3043) ../../example_design/transceiver.v(970): Unresolved reference to 'RX_LOS_THRESHOLD' in GT11_1XFC_2_INST.RX_LOS_THRESHOLD. 

 # Region: /testbench/DUT/transceivers_i


The problem is that the RX_LOS_INVALID_INCR and RX_LOS_THRESHOLD signals have been removed from the Virtex-4 GT11 SmartModels in 7.1i Service Pack 3. 


A patch is available to resolve this issue. To obtain this fix, please install the patch that is available in the LogiCORE Fibre Channel v2.0 Core Release Notes and Known Issues Answer Record (Xilinx Answer 21048) and then regenerate the core.

AR# 21665
Date 05/19/2014
Status Archive
Type General Article
Page Bookmarked