We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21681

Spartan-3E PAR - "ERROR:Place:311 - The IOB <signal_name> is locked to site PAD2 in bank 0. This violates the SelectIO banking rules."


Keywords: locking, LVCMOS15, illegal placement, violation

When I lock an LVCMOS15 input in the same bank as an LVCMOS25 output, the following error message occurs:

"ERROR:Place:311 - The IOB outa is locked to site PAD2 in bank 0. This violates
the SelectIO banking rules. Other incompatible IOBs may be locked to the same
bank, or this IOB may be illegally locked to a Vref site.
ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design
cannot be automatically placed."

This should be a legal placement, as Spartan-3E inputs are no longer dependent on VCCO.


This is a legal placement in hardware. However, the software currently does not allow this placement. LVCMOS15, LVCMOS18, and LVCMOS25 inputs must be in a bank with a matching VCCO level. These overly restrictive banking rules are fixed in 9.1.03i. You can download Service Pack 3 at:

If you are using an earlier version of the software and need to place one of these standards in a bank with a higher VCCO level (for example, an LVCMOS25 input in a bank with VCCO=3.3V, or an LVCMOS15 input in a bank with VCCO = 2.5V), you can modify the IOSTANDARD in the FPGA Editor and run BitGen without the DRC check (bitgen -d). For more information on how you can work around this problem, contact Xilinx Technical Support at:

AR# 21681
Date 04/25/2007
Status Active
Type General Article