UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21682

8.1i XST - Known Issues

Description

Keywords: synthesis, synthesize, problems

This Answer Record contains Known Issues for XST 8.1i.

Solution

Q1. Can XST pass generics in the command line?
A1. This feature is not currently supported. Support for this feature is planned for ISE 9.1i.

Q2. Backward Register Balancing has no effect on carry chains.
A2. See (Xilinx Answer 21766).

Q3. Using disable constructs in "for loops" does not work.
A3. This is a known limitation in XST. Support for this is planned for ISE 9.1i.

Q4. The stop condition != is not supported in "for loops."
A4. See (Xilinx Answer 21806).

Q5. Expressions that evaluate to a real constant are not supported.
A5. This is a known limitation in XST. Support for this is planned for ISE 9.1i.

Q6. Using disable constructs in "for loops" does not work.
A6. This is a known limitation in XST. Support for this is planned for ISE 9.1i.

Q7. Signed input in case statements is not supported.
A7. This is a known limitation in XST. Support for this is planned for ISE 9.1i.

Q8. Hex input in case statements is not supported.
A8. This is a known limitation in XST. Support for this is planned for ISE 9.1i.

Q9. Hierarchical defparam is not supported.
A9. This is a known limitation in XST. Support for this is planned for ISE 9.1i.

Q10. The Verilog "wait" statement is not supported.
A10. This is a known limitation in XST. There is no fix scheduled for this issue.

Q11. XST does not reject size mismatch in assignment.
A11. This is a known limitation in XST. Support for this is planned for ISE 9.1i.

Q12. "WARNING:Xst:819 - file.vhd Line xx: The following signals are missing in the process sensitivity list..."
A12. See (Xilinx Answer 14310).

Q13. An unconstrained integer results in bad quality.
A13. This is a known limitation in XST. Support for this is planned for ISE 9.1i.

Q14. "ERROR:Xst:783 - top.vhd line 12: Matrix not supported yet."
A14. See (Xilinx Answer 14649).

Q15. Declaring constants in one package and assigning them in another is not supported.
A15. This is a known limitation in XST. No fix is scheduled for this issue.

Q16. A nested "for loop" in VHDL is not supported.
A16. This is a known limitation in XST. No fix is scheduled for this issue.

Q17. The use of multiple wait conditions is not supported.
A17. This is a known limitation in XST. No fix is scheduled for this issue.

Q18. When an attribute in the XCF is modified, XST does not recognize the change, even if it appears in the log file.
A18. This is a known limitation in XST. Support for this is planned for ISE 8.2i.

Q19. Use of the same integer variable for two separate loops generates an incorrect netlist.
A19. See (Xilinx Answer 22066).

Q20. "ERROR:HDLParsers:818 - Cannot determine the type of the selector &"
A20. See (Xilinx Answer 22098).

Q21. Use of the same integer variable for two separate loops generates an incorrect netlist.
A21. See (Xilinx Answer 22066).

Q22. Does XST support Verilog-specific blocks?
A22. See (Xilinx Answer 22171).

Q23. "INTERNAL_ERROR:Xst:cmain.c:3068:1.158.12.1 - Creating DSP functions."
A23. See (Xilinx Answer 22167).

Q24. "ERROR:Xst:2088 Disable statement not supported in a for loop."
A24. See (Xilinx Answer 22177).

Q25. XST does not support ifdefs in meta comments.
A25. See (Xilinx Answer 22227).

Q26. "FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13.276.1."
A26. See (Xilinx Answer 22271).

Q27. Distributed RAM with a bus_delimiter set to [] causes incorrect behavior.
A27. See (Xilinx Answer 22360).

Q28. "ERROR:Xst:1923 - Line <MY_LINE> has not enough elements for target <MY_DATA>"
A28. See (Xilinx Answer 22376).

Q29. Virtex/-E, Spartan-II/E - Dual-Port Dual-Write RAM Inference does not work as shown in the XST User Guide.
A29. See (Xilinx Answer 22385).

Q30. "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, and WEA3 of RAMB16 symbol "<symbol_name>" do not share the same signal. When WRITE_WIDTH_A is set to 1, 2, 4, or 9, these pins should be connected to the same signal."
A30. See (Xilinx Answer 22397).

Q31. Is the package NUMERIC_SIGNED supported?
A31. See (Xilinx Answer 22425).

Q32. What does "ERROR:Xst:772 - "Attribute is not authorized : 'succ'." mean?
A32. See (Xilinx Answer 22495).

Q33. Inverters are missing in the RTL View.
A33. See (Xilinx Answer 22402).

Q34. Spartan-3/E synthesis design reports DCM_ADV instead of DCM.
A34. See (Xilinx Answer 22623).

Q35. "ERROR:Xst:787 - "<filename>.vhd" line 263: Index value <8> is not in Range of array <$n0004>""
A35. See (Xilinx Answer 22624).

Q36. XST runs out of memory or takes a long time to synthesize with designs having nested for loops.
A36. See (Xilinx Answer 22625).

Q37. XST has problems dealing with two values in a case statement that leads to the same output value.
A37. See (Xilinx Answer 22637).

Q38. XST is not inferring the correct reset logic for next_state when it is reset in a two-process FSM.
A38. See (Xilinx Answer 22654).

Q39. XST generates incorrect logic when concatenating a 2-bit vector with a 14-bit vector and muxing for a 16-bit vector.
A39. See (Xilinx Answer 22684).

Q40. XST generates incorrect logic for code that infers ROM in other synthesis tools.
A40. See (Xilinx Answer 22741).

Q41. XST generates incorrect logic for VHDL code that assigns a bus bit-by-bit.
A41. See (Xilinx Answer 22753).

Q42. FSM is not getting encoded by XST when there is no initial condition.
A42. See (Xilinx Answer 22761).

Q43. XST produces a warning " WARNING:Xst:647 - "unable to assign to aggregate signals and writes out incorrect logic.
A43. See (Xilinx Answer 22811).

Q44. "ERROR:HDLParsers:3338 - "<...>" Line 1. Bad file name in project file: Env Variable <...> not defined."
A44. See (Xilinx Answer 22726).

Q45. Subtraction of integer values is incorrect when one operand is negative.
A45. See (Xilinx Answer 23049).

Q46. XST - "WARNING:HDLParsers:3530 - Time stamp of file <name_of file>.vhd is newer than the current system time."
A46. See (Xilinx Answer 23050).

Q47. Duplicated flip-flop does not adhere to default duplication suffix.
A47. See (Xilinx Answer 23063).

Q48. XST is stripping out the commas in my NGC file and causing MAP to fail
A48. See (Xilinx Answer 23057).

Q49. ERROR:HDLParsers:3501 - Circular dependency is not supported!
A49. See (Xilinx Answer 23141).

Q50. Warning "Xst:2183: the following tristate(s) are NOT replaced by logic" - Reasons XST cannot replace TBUFs with logic
A50. See (Xilinx Answer 20048)

Q51. XST fails to report the correct number of block RAMs in the design.
A51. This is a known issue with XST and this is why the MAP report should be used to get the most accurate number. This issue will be fixed in ISE 9.1i.

Q52. XST has a problem mapping I/O Flip-Flop and RESET inside IOB in certain cases
A52. See (Xilinx Answer 23273)

Q53. "ERROR:Xst:2033 - Port I of Input buffer <instance_name> is connected to GND" when using IOBUFDS
A53. See (Xilinx Answer 23315)

Q54. With same primitive instantiated in a mixed language flow "_1" is added in the netlist primitive name that causes the design to error out in NGDBuild
A54. See (Xilinx Answer 23317)

Q55. ERROR:HDLParsers:808 - "C:/.../des.vhd" Line 599. TO_INTEGER can not have such operands in this context."
A55. See (Xilinx Answer 23309)

Q56. XST generates incorrect logic when an integer type is used in a record type in VHDL
A56. See (Xilinx Answer 23334)
AR# 21682
Date Created 09/04/2007
Last Updated 01/07/2009
Status Archive
Type General Article