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AR# 21697

LogiCORE SPI-3 (POS-PHY L3) - How are the SPI-3 cores affected by the new Virtex-4 DCM parameter requirements?

Description

General Description: 

How are the SPI-3 cores affected by the new Virtex-4 DCM parameter requirements? 

 

The requirements of the new DCM parameters for Virtex-4 are explained in (Xilinx Answer 21127).

Solution

The SPI-3 Link Layer Core v2.x with fixed channel netlists (1-ch, 2-ch, 4-ch) cores do not support the Virtex-4 Family; therefore, these cores are not affected. 

 

The SPI-3 Link Layer Core v3.2 with multi-channel support does NOT contain embedded DCMs within the core; therefore, the core itself is not affected. However, the design example does contain DCMs in the top-level design file, which will be affected if you were to use this design example in hardware. The files that contain DCMs are: 

 

/pl3_link_v3_2/virtex2/implement/verilog/pl3_link_top.v  

 

and 

 

/pl3_link_v3_2/virtex2/implement/vhdl/pl3_link_top.vhd 

 

The two DCMs used in the top-level design file are called "TFClk_dcm0" and "RFClk_dcm0". If you would like to use these files for board-level testing, see (Xilinx Answer 21127) to incorporate the DCM_STANDBY macro for each DCM used within the design.

AR# 21697
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article